1. Field of the Invention
The present invention relates to a semiconductor device having a trench isolation structure. More particularly, the present invention relates to a semiconductor device such as a CMOS device having multiple power supply voltages and using trench isolation for element isolation structure.
2. Description of the Related Art
In a semiconductor device having CMOS devices which use multiple power supply voltages, it is important to improve degree of integration of low power supply voltage sections forming an internal circuit such as a logic circuit and, at the same time, to secure latch-up resistance of high power supply voltage sections used for input/output circuits or the like.
Element isolation is often carried out by trench isolation method which is more suitable for higher integration than LOCOS method. However, in a semiconductor device whose element isolation is carried out by trench isolation, in order to secure enough latch-up resistance for high power supply voltage circuit sections, it is necessary to increase the depth of a well to suppress parasitic bipolar action, and, in order to reduce leakage current between an NMOS transistor and a PMOS transistor and to secure high voltage withstanding characteristics, it is necessary to make the isolation width of a trench isolation portion larger. Accordingly, there is a problem that, when the low power supply voltage circuit sections use the same trench isolation as that of the high power supply voltage circuit sections, the degree of integration of elements reduces in the low power supply voltage sections to which high degree of integration is required.
As measures for improvement thereof, a method of making the depth of a well in the high power supply voltage circuit section larger than that of a well in the low power supply voltage circuit section and making the width of a trench isolation portion in the high power supply voltage circuit section larger than that of a trench isolation portion in the low power supply voltage circuit section is proposed (see Japanese Patent Laid-open Application JP2000-58673A, for example).
As described above, in a semiconductor device which uses multiple power supply voltages where element isolation is carried out by trench isolation, in order to secure enough latch-up resistance for a high power supply voltage circuit section, it is necessary to increase the depth of a well to suppress parasitic bipolar action, and, in order to reduce leakage current between an NMOS transistor and a PMOS transistor and to secure high voltage withstanding characteristic, it is necessary to make the width of a trench isolation portion larger. Accordingly, there is a problem that, when the low power supply voltage circuit section uses the same trench isolation as that of the high power supply voltage circuit section, the degree of integration of elements reduces in the low power supply voltage section to which high degree of integration is required.
The examples in which the depth of a well in the high power supply voltage circuit section is made larger than that of a well in the low power supply voltage circuit section and the width of a trench isolation portion in the high power supply voltage circuit section is made larger than that in the low power supply voltage circuit section have been proposed, however, there are problems that the number of the manufacturing steps increases and that the increase in the width of a trench isolation portion leads to increase in cost.